Random hardware faults cause integrated circuit (IC) devices to malfunction in ways that are difficult to prevent. The phrase “random hardware faults” is typically used to reference a wide range of defects that cause individual gates of an IC device to fail, thereby producing erroneous data that causes the IC device to malfunction (i.e., to perform its intended functionality). Random hardware faults can either be age-related, or caused by events that cause IC devices to malfunction prematurely. Age-related random faults (e.g., transistor failures caused by the migration/merging of dopants within the semiconductor substrates) are expected to occur in all ICs eventually, and are easily anticipated and prevented by way of scheduled replacement of IC devices before the end of their operating lifetimes). In contrast, premature random faults cause IC devices to unexpectedly malfunction (e.g., fail entirely or continue to operate but generate erroneous data) during their expected operating lifetime. Due to the development of highly sophisticated EDA software tools, such as those produced by Synopsys, Inc., premature random faults rarely occur in modern IC devices, but can result from a wide range of accidental or randomly occurring causes, such as operation of ICs at temperatures outside of their specified operating ranges, or inadvertent exposure of ICs to hazardous environmental conditions such as radiation, which can cause damage due to alpha-particle hits. As used herein, the phrase “random hardware fault(s)” or “random fault(s)” is used primarily with reference to premature random faults.
Conventional fault detection circuits are utilized in some IC devices to detect random hardware faults where the consequences of premature random hardware faults can be significant. Premature random hardware faults occur at such a low probability that they are typically ignored in IC devices utilized in non-critical systems (e.g., systems in which the occurrence of random hardware faults does not pose a serious health risk to the user). However, the cost of incorporating fault detection circuits into IC devices typically outweighs potential liabilities when the IC circuits are utilized in critical (e.g., mission-critical or safety-critical) devices/systems, where erroneous data generated by the critical circuits/devices can cause significant financial loss and/or serious injury. When combined with fault mitigation circuitry that, for example, automatically reconfigures host IC circuit to re-route data from circuitry affected by a random hardware fault to known-good redundant circuitry, the use of fault detection circuits avoids the potentially significant consequences caused by premature random hardware faults.
A problem with existing conventional fault detection circuits is that they cannot be incorporated into configuration data paths utilized in some critical circuits/devices. That is, some control IC devices utilized in automotive, aerospace, and industrial applications utilize memory-mapped configuration registers to store data utilized to configure associated mechanisms. For example, an aileron-control circuit may include a processor that utilizes sensor input data to calculate data defining optimal positions for ailerons provided on an aircraft's wings, whereby the processor periodically repositions the ailerons by way of periodically writing updated optimal aileron position (configuration) data into one or more configuration registers that are operably linked to positioning motors respectively attached to the ailerons. That is, the aileron positioning motors fix the ailerons' positions in accordance with the configuration data stored in (and transmitted to the motors from) the configuration register(s) at any given moment, whereby the aileron positioning motors reposition the ailerons each time the processor writes updated (new/different) configuration data into the configuration register(s). In this situation, the reliable detection of random hardware faults that may occur in the signal path between the processor and the positioning motors (e.g., in the configuration register) could critically affect safe operation of the aircraft. Unfortunately, currently available conventional fault detection circuits cannot be utilized to detect random hardware faults occurring in configuration registers. That is, most conventional fault detection circuits mainly focus on counter/shifter circuits and adder circuits in a way that is inconsistent with configuration register operations. Some conventional fault detection circuits require a special low frequency clock and/or other special control circuitry that would require significant reconfiguration of the control circuitry utilized to control data input into the configuration register(s). Other conventional fault detection circuits are configured for use in register-files, which are a type of fixed-size memory, and utilize duplication approaches that are only for narrow-width values and require significant chip area to implement. Moreover, none of the existing fault detection circuits includes a self-text function that verifies proper operation of the fault detection circuit.
What is needed is a scalable fault detection circuit capable of reliably detecting random hardware faults occurring in configuration registers and can be easily integrated into existing IP/IC (circuit designs) and address the problems set forth above.